Presentation

RISC-V@BSC: Paving the Way for Overcoming HPC Workloads Challenges
DescriptionRISC-V is an open standard Instruction Set Architecture (ISA) enabling a new era of processor innovation through open collaboration. It brings new opportunities for researchers and industry to go further than any time before; and Barcelona Supercomputing Center (BSC-CNS) is a good example of that within the High-Performance-Computing domain.
BSC-CNS is one of the most relevant European HPC research centers, which actively promotes the adoption, design and development of solutions based on RISC-V as an alternative to non-European vendors. Nowadays HPC is playing a key role in our modern world, not only for accelerating traditional complex applications, but also emerging ones. In addition, application domains for HPC are more diverse, and they are not limited to supercomputers. Day by day, HPC is more strategic for socioeconomical sectors such as industry 4.0 and/or automotive, just to mention some. In this direction, BSC is actively involved in multiple activities aiming to foster collaboration and paving the way for overcoming some of the current challenges that powerful workloads are facing.
This talk shows a landscape of RISC-V initiatives at BSC, and how those might potentially impact and benefit HPC workloads and potentially how to use and program those to run in future supercomputers.
SlidesPDF
TimeTuesday, June 411:30 - 12:00 CEST
LocationHG E 1.2
Session Chair
Event Type
Minisymposium
Domains
Computational Methods and Applied Mathematics