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UID:submissions.pasc-conference.org_PASC24_sess118_msa177@linklings.com
SUMMARY:Hardware Acceleration for Hard Event Generation
DESCRIPTION:Minisymposium\n\nZenny Wettersten (CERN, TU Wien)\n\nThe first
  step in the particle physics simulation chain involves the evaluation of 
 exact, analytic scattering amplitudes in a process called hard event gener
 ation. Although these amplitudes are given by explicit mathematical expres
 sions, their complexity alongside the sheer magnitude of necessary evaluat
 ions make them a noteworthy bottleneck for LHC computing purposes; and unl
 ike other simulation bottlenecks, which often involve a significantly bran
 ching control flow, scattering amplitude evaluations are computed identica
 lly across many different phase space points. As such, hard event generati
 on is a well-suited task for data-level parallelism. In the last few years
 , a working group of data scientists and physicists across Europe and the 
 US have worked on porting leading order (LO) hard event generation within 
 the particle physics framework MadGraph5_aMC@NLO (MG5aMC) to SIMD/SIMT arc
 hitectures, such as vector CPUs and GPUs, and recently work has been start
 ed on additionally parallelising next-to-leading order (NLO) corrections t
 o these amplitudes. This involves significant restructuring and rewriting 
 of legacy code, but has proven fruitful. Preliminary tests for LO event ge
 neration often show maximal theoretical speedup found when compared to nat
 ive MG5aMC, and there is ongoing work to integrate this software into the 
 LHC experiments’ simulation chains.\n\nDomain: Engineering, Physics, Compu
 tational Methods and Applied Mathematics\n\nSession Chair: Katherine Royst
 on (Oak Ridge National Laboratory)
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