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UID:submissions.pasc-conference.org_PASC24_sess120_msa272@linklings.com
SUMMARY:RISC-V@BSC: Paving the Way for Overcoming HPC Workloads Challenges
DESCRIPTION:Minisymposium\n\nTeresa Cervero (Barcelona Supercomputing Cent
 er)\n\nRISC-V is an open standard Instruction Set Architecture (ISA) enabl
 ing a new era of processor innovation through open collaboration. It bring
 s new opportunities for researchers and industry to go further than any ti
 me before; and Barcelona Supercomputing Center (BSC-CNS) is a good example
  of that within the High-Performance-Computing domain. \nBSC-CNS is one of
  the most relevant European HPC research centers, which actively promotes 
 the adoption, design and development of solutions based on RISC-V as an al
 ternative to non-European vendors. Nowadays HPC is playing a key role in o
 ur modern world, not only for accelerating traditional complex application
 s, but also emerging ones. In addition, application domains for HPC are mo
 re diverse, and they are not limited to supercomputers. Day by day, HPC is
  more strategic for socioeconomical sectors such as industry 4.0 and/or au
 tomotive, just to mention some. In this direction, BSC is actively involve
 d in multiple activities aiming to foster collaboration and paving the way
  for overcoming some of the current challenges that powerful workloads are
  facing. \nThis talk shows a landscape of RISC-V initiatives at BSC, and h
 ow those might potentially impact and benefit HPC workloads and potentiall
 y how to use and program those to run in future supercomputers.\n\nDomain:
  Computational Methods and Applied Mathematics\n\nSession Chair: Nick Brow
 n (EPCC)
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