BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:Europe/Stockholm
X-LIC-LOCATION:Europe/Stockholm
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=-1SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=10;BYDAY=-1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20241120T082410Z
LOCATION:HG F 30 Audi Max
DTSTART;TZID=Europe/Stockholm:20240603T190500
DTEND;TZID=Europe/Stockholm:20240603T190600
UID:submissions.pasc-conference.org_PASC24_sess156_pos134@linklings.com
SUMMARY:P15 - Enabling Message-Driven Architecture Evaluation for the Extr
 eme Heterogeneity Era with MOSAIC
DESCRIPTION:Poster\n\nPatricia Gonzalez-Guerrero and Anastasiia Butko (Law
 rence Berkeley National Laboratory); Chris Neely (AMD); and Farzad Fatolla
 hi-Fard, Jordi Wolfson-Pou, Mario Vega, Thom Popovici, and John Shalf (Law
 rence Berkeley National Laboratory)\n\nMassive parallelism and extreme het
 erogeneity are key to enabling futuristic exascale high-performance comput
 ing (HPC). Parallelism usually involves a shared-memory model with hardwar
 e-based cache-coherence mechanisms that enforce atomicity, ensuring transp
 arent data movement and memory consistency. However, as the levels of para
 llelism (up to 100M cores) and heterogeneity increase, the scalability of 
 cache coherence protocols is compromised due to (i) extensive protocol-rel
 ated traffic, (ii) unique memory requirements of specialized architectures
 /accelerators, and (iii) the high latency (+100 clock cycles) associated w
 ith atomic operations. We propose to use hardware message queues (HMQs) wh
 ich might be the key for practical massive parallelism and extreme heterog
 eneity. First, HMQs offer a low-latency direct path for inter-node communi
 cation that bypasses expensive cache-coherence protocols. Second and contr
 ary to general-purpose cache-coherence systems, the same HMQ mechanisms ca
 n be used for general-purpose cores such as RISCVs or kick-start computati
 on in specialized accelerators such as Fast Fourier Transform. In this wor
 k, we propose MOSAIC, a full-stack platform to facilitate the evaluation a
 nd design space exploration of HMQs in heterogeneous architectures. Since 
 field programmable arrays (FPGAs) provide a cost-effective testbed for har
 dware exploration, we aim at an extremely lightweight, flexible architectu
 re optimized for FPGA. However, MOSAIC could also target chiplets or SoC/A
 SIC.\n\nSession Chair: Erik W. Draeger (Lawrence Livermore National Labora
 tory)
END:VEVENT
END:VCALENDAR
